Output Triggering Technology
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One-Shot Triggering with Single-Sample Updating
This configuration begins generation of a timed output signal when an external triggering signal arrives. When clocking, one update is delivered to the analog output on each clock pulse.
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Output triggering is a standard feature on all Data Acquisition Processor models that support digital to analog conversion. |
Notes:
- Clock source can be external (
extClk) or internal onboard (iClk) - Trigger starts low, and must be held active high at least
tTrigMin - For external clocks, the clock cycle must be at least
tSynch + TIME specification - All clock levels must be held for at least
tExtClkPW - Clocking activity begins
tTCsetupafter triggering goes active - Data from buffer must be fetched and stable at converter before clocking
- Update values latched for conversion at clock edges
- Analog output values stabilize after settling transient
- Unless you configure burst mode, one-shot triggering responds only once