It all depends on what your application does. There are subtle timing differences that might be important, or might not.

The galvanic isolation of the MSXB078 boards simply means that power and information move through an insulation layer that blocks any direct flow of current. This allows the external I/O lines and the DAP digital bus lines to operate at displaced voltage levels and avoid unintended interaction through a common direct connection. A physical process is required to transport information via encodings on the electromagnetic fields, and this process has subtle effects on timing delays and jitter.

For digital outputs, these timing effects are typically small enough to be irrelevant. The DAP sends the bits out; shortly thereafter, the values of the bits become externally visible. No change is required to the processing logic.

However, for digital inputs, there is a larger timing hazard. Two steps are required: the first latches the bit values, and the second presents the results of the data to the DAP I/O bus on the other side of the barrier. If these things were done in strict sequence, the MSXB078 board would operate the same as the MSXB038, but it would be much slower. To improve the data transfer rate, the MSXB078 performs operations in parallel. When the DAP addresses the MSXB078 board to transfer a 16-bit digital input bit values across the barrier to the digital data bus, at the same time, this also triggers the capture of the next 16 bits on the isolated side of the barrier.

This parallelization is known as pipelining. Did you notice the timing hazard? When the DAP says "put the digital data on the bus," the data it will receive is the data captured on the other side of the barrier on the previous I/O clock cycle. The data for the current clock cycle will not become visible until next I/O clock cycle. For lots of processes, the one-sample delay in observing digital signal changes makes no difference because the sample rate is already very fast.

There are other applications for which this delay in the sample clocking is critical.

• Example: you are using software triggering, and you need to capture the digital port bits at the time that an event is detected. The values reported from the digital port will actually be for the time before the event, not the time at the event, so information could be missed. Knowing that this will happen, the processing configuration can be modified to skip the stale digital reading and record the next one.

• Example: you are using hardware burst-mode triggering to capture the digital bits each time an external trigger pulse arrives. With the MSXB078 board, the value you get in response to the trigger pulse is the result from the previous trigger event, an indeterminate time in the past. Knowing that this is going to happen, the processing configuration can be modified to read two samples in response to the event, and discard the meaningless first value.

Consequently, for most processing that runs continuously, the subtle time delays from the digital input pipelining on the MSXB078 are too small to make any difference. But applications that are timing-critical, particularly those that take data selectively using some kind of triggering, will probably require adjustments to the processing software.